Tight Bounds on Expected Time to Add Correctly and Add Mostly Correctly

We consider the problem of adding two n-bit numbers which are chosen independently and uniformly at random where the adder is a circuit of AND, OR, and NOT gates of fan-in two. The fastest currently known worst-case adder has running time logn +O( p logn) [Khr]. We rst present a circuit which adds at least 1 fraction of pairs of numbers correctly and has running time log log ( n ) +O( p log log ( n )). We then prove that this running time is optimal. Next we present a circuit which always produces the correct answer. We show this circuit adds two n-bit numbers from the uniform distribution in expected 1 2 logn+ O( p logn) time, a speed up factor of two over the best possible running time of a worst-case adder. We prove that this expected running time is optimal. Computer Science Division, UC Berkeley, CA 94720. Supported by NSF grant number CCR-9201092. y Computer Science Division, UC Berkeley, CA 94720. Supported by National Physical Science Consortium (NPSC) Fellowship. Also supported by NSF grant number CCR-9201092